The present invention relates to a semiconductor memory device such as an EEPROM and, more specifically, to a redundant memory test circuit for testing a redundant memory of the device.
FIG. 11 is a block diagram showing an example of an arrangement of an address control circuit of a conventional semiconductor memory. The address control circuit includes a redundant control circuit. In this circuit, an input buffer 1 receives an address signal (Add) from outside through an I/O pin (not shown). An internal address signal generation circuit 2 includes a multiplexer and an address counter (not shown). Upon receiving the address signal from the input buffer 1, the multiplexer sets the address signal to the address counter as an access start address. The circuit 2 generates internal address signals A1 to A3 based on the access start address.
An address decoder 3 accesses a memory cell array (not shown), while a redundant address decoder 4 does a redundant memory cell array (not shown). A defective address storage circuit 5 has a fuse element group for storing defective address signals (fuse data) of the memory cell array. An address comparison circuit 6 compares the defective address signals stored in the circuit 5 and the internal address signals output from the internal address signal generation circuit 2, and controls the address decoder 3 and redundant address decoder 4 based on the comparison results.
To access the memory cell array in the address control circuit so arranged, an externally-input access start address is usually set in the address counter of the internal address signal generation circuit 2 through the input buffer 1.
The address counter counts up addresses in synchronization with read and write pulses supplied from outside and generates the address signals A1 to A3 (which are encoded in accordance with address values) having the number of bits according to an address space.
The address decoder 3 includes a row decoder and a column decoder, and these decoders decode the internal address signals to select a word line and a bit line corresponding to an address.
The address comparison circuit 6 compares the defective address signals and the internal address signals. When they coincide with each other, the circuit 6 outputs both a select inhibit signal SIS for setting the memory cell array in a nonselective state and a select signal /SS (/ indicates an inverted signal hereinafter) for setting the redundant memory cell array in a selective state. The select inhibit signal SIS is supplied to the address decoder 3, and the select signal /SS is supplied to the redundant address decoder 4. Thus, a defective block (defective row or defective column) of the memory cell array is replaced with a redundant block (redundant row or redundant column) of the redundant memory cell array.
FIG. 12 illustrates an example of the address comparison circuit 6 and the defective address storage circuit of FIG. 11. This example is adapted to a plurality of redundant address decoders 4 and, in other words, a plurality of address comparison circuits 62 to 64 are provided to compare a plurality of redundant addresses. A logic circuit 65 is also provided at the output terminals of the comparison circuits 62 to 64 to receive output signals /SRD1 to /SRD3 of these circuits 62 to 64.
The logic circuit 65 supplies the output signals /SRD1 to /SRD3 to the plural redundant address decoders 4 as select signals /SS (enable signals). Further, the circuit 65 includes a NAND gate 66 supplied with the output signals /SRD1 to /SRD3. The NAND gate 66 sends a select inhibit signal SIS (disable signal) to the address decoder 3 when at least one of the output signals /SRD1 to /SRD3 is activated.
In each of the comparison circuits 62 to 64, (A1, /A1), (A2, /A2), and (A3, /A3) are signals of bits constituting the internal address signals and their complementary signals, and they are supplied to the gates of N-channel MOS transistors Q, respectively. A fuse F is connected in series to each of the transistors Q to form a discharge pass. These transistors Q and fuses F constitute series circuits, and these circuits are each connected between a node N and a ground potential Vss and in parallel with each other. A charge pass of a P-channel MOS transistor P whose gate is supplied with a precharge signal PRE, is connected between each of the node N and a power supply potential Vcc.
The discharge passes are set so as to cause a current i2, which is larger than a current i1 of the discharge pass, to flow through the node N. The fuses F are blown or unburned in accordance with the content of each bit of the defective address signal. The potential of the node N is inverted by an inverter circuit IV and supplied as the above output signal /SRDi (i=1, 2 and 3).
If none of the fuses F are blown, at least one discharge pass is formed and thus the node N is set at a ground potential Vss (low level).
In the case shown in FIG. 13 where some fuses F are blown, if there is one difference between the content of each bit of data set in the plural fuses F and that of each of bit signals A1, /A1, A2, /A2, A3 and /A3, at least one discharge pass is formed. In other words, since no fuse is blown in the transistor supplied with the bit signal A1 of high level, a discharge pass is formed in the series circuit and thus the node N is set at a low level.
In contrast, as illustrated in FIG. 14, when the contents of bits of fuse data all coincide with those of bit signals A1, /A1, A2, /A2, A3 and /A3, no discharge pass is formed and thus the node N is set at the power supply potential Vcc (high level). If the node N is set at the high level, the address decoder 3 is disabled and the redundant address decoder 4 is enabled. A defective block of the memory cell array is therefore replaced with a redundant block.
In the foregoing semiconductor memory, when a defective block is detected from the memory cell array in a test during its manufacturing, a fuse F (e.g., polysilicon fuse) is blown. Thus, an intrinsic defective (incapable of a basic operation such as erase, write and read operations) can be removed from the memory cell array, and a memory device can be finished as a defect-free one.
If, however, a defective block is replaced with a redundant one in order to evaluate a device (chip or chip area) in detail during the development or manufacturing of memories, a fuse F has to be blown as described above. To blow the fuse, however, an apparatus exclusively for blowing a fuse or a laser beam is required, resulting in time and trouble in evaluating the device.
It is preferable that a device be changed into a completely defect-free one by replacing a defective block with a redundant block. If, however, there are a number of defective blocks, all of them are not replaced with redundant ones but some intrinsic defects remain. Since yields are low at an early stage of development of memories, a reliability test cannot be carried out sufficiently only by the defect-free devices. It is thus necessary to conduct a reliability test using chips including intrinsic defects; however, reliability defects and intrinsic defects are mixed with each other and thus only the reliability defects are difficult to extract.
The number of intrinsic defects is small at the stage where the yields of memories become stable. The reliability is evaluated after a fuse F is blown to replace a defective block with a redundant block. If, however, the fuse F is blown once, an address is switched automatically in a memory to perform the replacement. It is thus impossible to know how defective a cell is before it is replaced. If an erase voltage or a write voltage is decreased in an operation mode of a memory for accessing a defective cell before it is replaced or in an operation for erasing/writing all data from/to a chip in an EEPROM, it cannot be checked whether the voltage decrease is due to a defective cell which has not yet been replaced.
If a fuse F is blown and a defective block is replaced with a redundant one, defective data before the replacement cannot be reproduced. If, therefore, a defect is present in a redundant block, it is difficult to detect whether the memory cell array or the redundant circuit is defective. Consequently, the analysis of defects in a memory is difficult or delayed.